The present invention relates to a method for measuring the lifetime of a semiconductor integrated circuit, including MOS devices like MOS transistors, and also relates to a method for reliability testing of the circuit.
A semiconductor integrated circuit is made up of various types of circuit elements. Among other things, the lifetime of an MOS transistor, one of those types of circuit elements, has an important effect on the reliability of the circuit.
In recent years, as the number of devices integrated in a single semiconductor integrated circuit has been increased, a gate insulating film for an MOS transistor has been thinned considerably. Thus, the degradation of the gate insulating film determines the lifetime of the MOS transistor and eventually has a considerable effect on the lifetime of the circuit itself.
In evaluating the reliability of a semiconductor integrated circuit according to a known technique, an MOS capacitor under test, including a gate insulating film with a relatively wide area, is made in place of multiple small-sized MOS transistors included in the circuit. And the lifetime of the gate insulating film of the capacitor is predicted. That is to say, in the prior art, the reliability of a semiconductor integrated circuit has been evaluated on the supposition that the MOS capacitor including the gate insulating film with a relatively wide area is equivalent to the great number of small-sized MOS transistors.
For example, the lifetime of a semiconductor integrated circuit, made up of one hundred MOS transistors each having an area of 1 xcexcm2, has been regarded as equivalent to the lifetime of one MOS capacitor having an area of 100 xcexcm2. In other words, the lifetime of the circuit, made up of one hundred MOS transistors each having the area of 1 xcexcm2, has been believed a time it takes for a first one of the one hundred MOS transistors to cause a dielectric breakdown (i.e., the amount of leakage current flowing there exceeds its critical value). And the time has been believed equal to the lifetime of the MOS capacitor with the area of 100 xcexcm2, or a time it takes for the MOS capacitor to cause a dielectric breakdown.
Specifically, in an MOS transistor including a gate insulating film with a thickness of more than about 4 nm, a steep rise in leakage current, resulting from a stress placed on the transistor, i.e., the generation of hard breakdown (HBD), is identifiable. A gate insulating film with that thickness will be herein called a xe2x80x9cthick gate insulating filmxe2x80x9d. In this case, a time it takes for one of multiple MOS transistors in a semiconductor integrated circuit to cause the HBD may be estimated by using an MOS capacitor under test. And the estimated time may be regarded as the circuit""s lifetime.
However, as for an MOS transistor including a gate insulating film with a thickness of about 4 nm or less, i.e., a gate insulating film in which a direct tunneling current is prevailing, it is hard to identify the generation of the HBD. A gate insulating film with that thickness will be herein called a xe2x80x9cthin gate insulating filmxe2x80x9d.
That is to say, the thinner the gate insulating film of an MOS transistor, the less and less often the obvious dielectric breakdown is observable. Thus, the lifetime of a semiconductor integrated circuit cannot be predicted accurately enough.
In view of these respects, an object of the present invention is to predict the lifetime of a semiconductor integrated circuit accurately enough even when a thin gate insulating film is used for an MOS device.
To achieve this object, the present inventor carried out various types of researches on the lifetime of a semiconductor integrated circuit. As a result, I made the following findings.
If a stress is continuously placed on an MOS transistor including a gate insulating film with a thickness of about 6 nm or less, the generation of a soft breakdown (SBD) is identifiable. According to the accepted standards, the SBD refers to a state where the dielectric breakdown has not occurred yet. However, a very small amount of leakage current flows through a gate insulating film in the SBD state. Specifically, the SBD herein means a phenomenon that the density of leakage current, flowing locally through a particular region of the gate insulating film, has increased 100 times or more compared to the density before the stress is placed and is now greater than the density of leakage current flowing through any other region. As for an MOS transistor including a gate insulating film with a thickness of more than about 6 nm, it is difficult to identify the generation of the SBD separately from the HBD. This is because when the conditions of SBD generation are met by the transistor, the HBD and SBD much more likely occur at a time in that transistor.
Hereinafter, the SBD will be described with reference to FIG. 1.
FIG. 1 is a graph illustrating variations of gate current-gate voltage (IGxe2x88x92VG) characteristics obtained by repeatedly applying a constant voltage stress to an MOS capacitor including a gate insulating film with a thickness of 2.4 nm and an area of 0.01 mm2.
As shown in FIG. 1, once the stress voltage is applied, the IGxe2x88x92VG characteristic changes from its initial state initial where the direct tunneling current is prevailing into a B-SILC state. In the B-SILC state, a B-mode stress induced leakage current, resulting from the generation of the SBD, flows through a local region of the gate insulating film. The B-mode stress induced leakage current will be herein called a xe2x80x9cB-SILC currentxe2x80x9d.
Also, as the stressing time passes, the B-SILC current increases. Accordingly, the IGxe2x88x92VG characteristic in the B-SILC state sequentially changes from the curve a into the curve d by way of the curves b and c.
E. Wu et al. reported in IEDM (1998) 187 that where the SBD has occurred in a region of an MOS transistor where the gate electrode overlaps with the source or drain region, the MOS transistor cannot operate anymore. That is to say, E. Wu et al. also regards a time it takes for one of multiple MOS transistors in a semiconductor integrated circuit to cause the SBD as the circuit""s lifetime. This approach will be herein called a xe2x80x9cfirst lifetime prediction approachxe2x80x9d.
Following is the conclusion of my analysis on the xe2x80x9cfirst lifetime prediction approachxe2x80x9d.
FIG. 2 illustrates relationships between the leakage current IG and stressing time where a constant voltage stress (CVS) of xe2x88x924.3 V was applied to two MOS capacitors (which will be herein called xe2x80x9csamples A and Bxe2x80x9d) formed on the same semiconductor substrate. It should be noted that xe2x80x9cxe2x88x92xe2x80x9d herein means that the gate electrode is at the lower potential level. Also, the samples A and B had gate insulating films with the same configuration (i.e., thickness: 2.4 nm; area: 0.01 mm2) and the stress was placed differently on the samples A and B. More specifically, even after the SBD generation had been identified, the stress was continuously imposed on the sample A. As for the sample B on the other hand, the instant the SBD generation was identified, the stressing was once suspended and then the stressing was started again. In FIG. 2, the graph plotted for sample B(1) illustrates a relationship between the leakage current and stressing time before the stressing was suspended. On the other hand, the graph plotted for sample B(2) illustrates a relationship between the leakage current and stressing time after the stressing was restarted.
As shown in FIG. 2, when the SBD occurs, the leakage current IG of the sample A rises steeply and then increases relatively gently. In contrast, after the stressing is restarted, the leakage current IG of the sample B (see the graph for the sample B(2)) increases gradually but is smaller than the leakage current IG of the sample A.
That is to say, the level of the leakage current IG flowing after the SBD generation changes greatly depending on whether or not the stress is continuously placed after the SBD has occurred. Thus, it can be seen that the amount of B-SILC current flowing after the SBD generation is not determined by the degradation occurred in the gate insulating film before the SBD generation, but by the degradation to occur in the same film after the SBD generation. Examples of the degradation of the former type include creation of defects in the film. And the degradation of the latter type will be herein called an xe2x80x9cinsulating film degradationxe2x80x9d.
It is believed that after the SBD has occurred, the insulating film degradation go on because of the following reasons. Specifically, if the charge, stored on the MOS capacitor due to the stress placed, flows through an SBD path being formed, then Jule heat is generated, thereby adversely expanding the SBD path and accelerating the insulating film degradation (see T. Sakura et al., IEDM (1998) 183). The SBD path is a conductive path causing the SBD in the gate insulating film. In this case, the quantity of charge stored on the MOS capacitor changes with the area or thickness of the gate insulating film or the stress voltage. Accordingly, the degree of insulating film degradation occurring after the SBD generation is also greatly dependent on the area or thickness of the gate insulating film or the stress voltage.
As described above, the data shown in FIG. 2 was obtained by applying the stress voltage with the absolute value of 4.3 V to the MOS capacitor including the gate insulating film with the area of 0.01 mm2. On the other hand, each of MOS transistors included in a semiconductor integrated circuit that should have its lifetime predicted (which will be herein called a xe2x80x9cactual devicexe2x80x9d) has a gate insulating film with an area of about 1 xcexcm2, for example. Also, a gate voltage applied to each MOS transistor under its actual operating conditions is about 1.5 V, for example. Accordingly, in the experiment carried out to obtain the data shown in FIG. 2, leakage current, corresponding to a charge quantity about 30,000 times as large as that of the actual device, flowed along the SBD path. However, the size of the SBD path being formed is not dependent on the area of the insulating film. Thus, even if the SBD has occurred at just one of the MOS transistors in the actual device, the amount of B-SILC current flowing through the gate insulating film would be too small to affect the operation of the transistor.
Next, a method of measuring the B-SILC current with a constant current stress (CCS) applied will be described with reference to the flowchart illustrated in FIG. 3.
In Step S1, stress current supplied to a sample like an MOS transistor, time interval at which it is determined whether the SBD occurred or not, and threshold value of voltage variation by which the SBD generation is identified are set to Istress [A], t [s] and r [%], respectively. The threshold value will be herein called a xe2x80x9cvariation threshold valuexe2x80x9d.
In Step S2, the stress current of Istress [A] starts to be supplied to the sample. Next, in Step S3, the magnitude of a stress voltage (i.e., a first voltage value V1) needed to supply the stress current of Istress [A] is measured. Then, in Step S4, the stress current of Istress [A] is continuously supplied for t seconds. Thereafter, in Step S5, the magnitude of a stress voltage (i.e., a second voltage value V2) needed to supply the stress current of Istress [A] is measured.
In Step S6, it is determined whether or not a ratio of the absolute value of the voltage variation V2xe2x88x92V1 between the second and first voltage values V2 and V1 to the first voltage value V1 has become equal to or greater than r %.
If the ratio of the absolute value of the voltage variation V2xe2x88x92V1 to the first voltage value V1 is less than r % (i.e., where the SBD has not occurred yet), then the first voltage value V1 is updated into the second voltage value V2 in Step S7. Then, the process returns to Step S4.
Alternatively, if the ratio of the absolute value of the voltage variation V2xe2x88x92V1 to the first voltage value V1 is r % or more (i.e., where the SBD has already occurred), then the stressing is suspended in Step S8. Thereafter, in Step S9, the total stressing time that has passed since the start of stressing is obtained as an SBD generation time (i.e., a time that has passed since the start of stressing and until the SBD generation) TSB. Then, in Step S10, the amount of leakage current flowing when a predetermined gate voltage is applied to the sample, i.e., the amount of B-SILC current IBSILC, is measured.
In the method of measuring the amount of B-SILC current as shown in FIG. 3, if the time interval of t [s] is shortened, then the stressing can be suspended almost simultaneously with the SBD generation. Thus, the insulating film degradation after the SBD generation can be suppressed to a certain degree as described above.
FIG. 4 is a graph illustrating a correlation between the amount of B-SILC current IBSILC, which was obtained by the B-SILC current measuring method shown in FIG. 3, and the amount of stress current Istress. In other words, FIG. 4 illustrates the stress condition dependence of the B-SILC current. The amount of B-SILC current IBSILC shown in FIG. 4 was measured by applying a gate voltage VG of xe2x88x921.5 V to an MOS capacitor, including a gate insulating film with a thickness of 2.4 nm and an area of 0.01 mm2, after the SBD had been generated there by supplying various stress currents thereto. Also shown in FIG. 4 is a variation in the amount of B-SILC current IBSILC where the gate voltage VG of xe2x88x921.5 V was continuously applied thereto for 100 seconds after the SBD had been generated.
As shown in FIG. 4, a correlation (see the dashed line) exists between the amounts of B-SILC and stress currents IBSILC and Istress. Specifically, the amount of B-SILC current IBSILC lightly depends on the amount of stress current Istress: the smaller the amount of stress current Istress, the smaller the amount of B-SILC current IBSILC. However, as also shown in FIG. 4, once the amount of stress current Istress exceeds a certain value, the B-SILC current IBSILC flows in the amount (between xe2x88x921 xcexcA and xe2x88x9210 xcexcA) greater than those represented by the dashed-line correlation.
FIG. 5 is a graph illustrating variations of IGxe2x88x92VG characteristics obtained by using the B-SILC current measuring method shown in FIG. 3 with the amount of stress current Istress changed. The IGxe2x88x92VG characteristics shown in FIG. 5 were obtained by applying various gate voltages VG to an MOS capacitor, including a gate insulating film with a thickness of 2.4 nm and an area of 0.01 mm2, after the SBD had been generated by supplying various stress currents thereto. In FIG. 5, the IGxe2x88x92VG characteristic for the range where the dashed-line correlation shown in FIG. 4 was met, i.e., the range where the amount of B-SILC current IBSILC for the gate voltage VG of xe2x88x921.5 V was smaller than 1 xcexcA (absolute value), is represented by the curve a. The IGxe2x88x92VG characteristic for the range where the correlation shown in FIG. 4 was not met, i.e., the range where the amount of B-SILC current IBSILC for the voltage VG of xe2x88x921.5 V was 1 xcexcA (absolute value) or more, is represented by the curve b or c. And the IGxe2x88x92VG characteristic before the stress was placed is represented the curve initial.
As for the IGxe2x88x92VG characteristic represented by the curve a in FIG. 5, the amount of gate current, i.e., the amount of leakage current, is at a negligible level for a transistor to operate properly. On the other hand, as for the IGxe2x88x92VG characteristic represented by the curve b or c in FIG. 5, the amount of leakage current reaches such a level as making the transistor inoperable. However, the amount of B-SILC current depends on a stress condition (e.g., stress current or stress voltage) as described above. Accordingly, it is believed that the leakage current flowing through an MOS transistor included in an actual device cannot reach the level as represented by the curve b or c in FIG. 5.
As described above, I believe that even if the SBD has occurred at just one of multiple MOS transistors in a semiconductor integrated circuit, the operation of the circuit itself would not be interfered with that. For that reason, if the lifetime of a semiconductor integrated circuit were predicted by the xe2x80x9cfirst lifetime prediction approachxe2x80x9d, the expected lifetime might be shorter than the actual one. Accordingly, if the thickness of a gate insulating film or a gate voltage for an MOS transistor is adjusted to equalize the lifetime predicted by the xe2x80x9cfirst lifetime prediction approachxe2x80x9d with a desired value (e.g., 10 years), the film could be excessively thick or the voltage could be unnecessarily low. As a result, the operating speed of the transistor decreases, thus considerably deteriorating the performance of the circuit.
As described in the xe2x80x9cbackground artxe2x80x9d, it is difficult to definitely identify the generation of the HBD in an MOS transistor including a thin gate insulating film.
So I supplied a new definition for the xe2x80x9cHBD generationxe2x80x9d. Specifically, I supposed that the lifetime of a semiconductor integrated circuit could be represented by a time it takes for one of multiple MOS transistors in the circuit to cause a newly defined HBD (which will be herein called a xe2x80x9credefined HBDxe2x80x9d). This alternative approach will be herein called a xe2x80x9csecond lifetime prediction approachxe2x80x9d.
Hereinafter, the conclusion of my analysis on the xe2x80x9csecond lifetime prediction approachxe2x80x9d will be described.
Even if the SBD has occurred in an MOS transistor, the amount of leakage current, i.e., gate current, is so small as represented by the curve d in FIG. 1, for example, that an inversion layer to be a channel for carriers can be formed under the gate insulating film.
However, considering the drain current-gate voltage (IDxe2x88x92VG) characteristic of an MOS transistor, the magnitude of a gate current at an operating voltage of 1.5 V (absolute value) should be equal to or less than a threshold value between several xcexcA and about 10 xcexcA to distinguish the ON/OFF states of the transistor from each other.
Thus, I regard the instant the magnitude of the gate current exceeds the threshold value as the instant the redefined HBD occurs.
FIG. 6 illustrates relationships between the leakage current IG and stressing time passed after the SBD generation where a constant voltage stress (CVS) of xe2x88x923.25 V was applied to an MOS capacitor including a gate insulating film with a thickness of 2.4 nm and an area of 0.01 mm2 after the SBD had occurred. The leakage currents shown in FIG. 6 were obtained by applying gate voltages VG of xe2x88x921.5 V and xe2x88x920.5 V to the MOS capacitor after the stress started to be placed. The SBD generation may be identified by the B-SILC current measuring method shown in FIG. 3.
As illustrated in FIG. 6, whether the voltage VG is xe2x88x921.5 V or xe2x88x920.5 V, the magnitude of the leakage current IG is almost constant until the point in time indicated by the dashed line. However, after the point in time indicated by the dashed line, the leakage current IG goes on increasing. Also, where the gate voltage VG is xe2x88x921.5 V, the leakage current IG changes almost continuously before and after the point in time indicated by the dashed line in FIG. 6. In contrast, where the gate voltage VG is xe2x88x920.5 V, the leakage current IG rises abruptly at the point in time indicated by the dashed line in FIG. 6.
To identify the generation of the redefined HBD, the instant the leakage current IG for the gate voltage VG of xe2x88x921.5 V exceeds the threshold value (i.e., on the order of several xcexcA to 10 xcexcA) should be located. However, as shown in FIG. 6, the threshold level exists in the range where the leakage current IG goes on increasing continuously. Thus, it is difficult to know exactly when the redefined HBD occurs. For that reason, I regard the point in time the leakage current IG for the gate voltage VG of xe2x88x920.5 V rises steeply as indicated by the dashed line in FIG. 6 as the instant the redefined HBD occurs. And the interval between the SBD generation and the redefined HBD generation (which will be herein called an xe2x80x9cHBD generation time THBxe2x80x9d) is obtained. FIG. 7 illustrates the dependence of the HBD generation time THB obtained this way on the stress voltage Vstress (which will be herein called xe2x80x9cstress voltage dependencexe2x80x9d). The data shown in FIG. 7 was obtained with the stress voltage Vstress applied at a temperature of 25xc2x0 C. Also illustrated in FIG. 7 is the stress voltage dependence of the SBD generation time TSB obtained by the B-SILC current measuring method shown in FIG. 3, for example.
As shown in FIG. 7, it is clear that the stress voltage dependence of the HBD generation time THB is different from that of the SBD generation time TSB. If the stress voltage Vstress is approximately equal to the actual operating voltage (e.g., about xe2x88x921.5 V), the HBD generation time THB is greater than the SBD generation time TSB by about five orders of magnitude or more. Accordingly, a time TBD it takes for an MOS capacitor to cause the redefined HBD is the sum of the SBD and HBD generation times TSB and THB strictly speaking, but can be essentially represented by the HBD generation time THB.
As described above, if the lifetime of a semiconductor integrated circuit is predicted by the xe2x80x9csecond lifetime prediction approachxe2x80x9d, then the circuit""s lifetime is substantially equal to the HBD generation time THB.
Furthermore, the longer the stressing time, the greater the B-SILC current resulting from the SBD generation and the greater the power dissipated. Thus, it becomes necessary to consider the power dissipated by the B-SILC current as a new factor limiting the lifetime of a semiconductor integrated circuit. In other words, the circuit""s lifetime should also be checked from this viewpoint, i.e., whether or not the power dissipated by the B-SILC current has exceeded an allowable value.
Thus, I supposed that the lifetime of a semiconductor integrated circuit could also be represented by a time it takes for a total amount of B-mode stress induced leakage currents, flowing through respective MOS transistors in the circuit, to reach a predetermined reference level. The reference level may be determined by the power dissipation specification of the circuit as a whole. This alternative approach will be herein called a xe2x80x9cthird lifetime prediction approachxe2x80x9d.
Hereinafter, the conclusion of my analysis on the xe2x80x9cthird lifetime prediction approachxe2x80x9d will be described.
According to the third lifetime prediction approach, the behaviors of respective MOS transistors in a semiconductor integrated circuit are all taken into account. That is to say, the degradation of the overall circuit changes depending on the number of SBD spots, i.e., spots where the SBD has occurred in the transistors. In the following description, the number of SBD spots will be represented by the number of transistors in each of which just one SBD spot exists (which transistor will be herein called an xe2x80x9cSBD transistorxe2x80x9d) for the sake of simplicity. Actually, a number of SBD spots should exist in a single transistor. Statistically speaking, though, the existence of 100 SBD spots in one transistor is equivalent to the existence of one SBD spot in each of one hundred transistors.
Suppose a number N (which is a natural number) of MOS transistors are included in a semiconductor integrated circuit implemented as a single semiconductor chip. The greater the number of SBD transistors among the number N of MOS transistors, the larger the total amount of B-mode stress induced leakage currents flowing through the circuit (which will be herein called a xe2x80x9ctotal leakage currentxe2x80x9d). In this case, the magnitude of B-mode stress induced leakage current flowing through one SBD spot (i.e., a single SBD transistor) would be smaller than the amount of reference leakage current required for the circuit in accordance with power dissipation specifications, for example. The amount of reference leakage current will be herein called a xe2x80x9creference levelxe2x80x9d. Accordingly, while the number of SBD transistors is still small, the total leakage current of the circuit is believed to be less than the reference level.
As described above, according to the xe2x80x9cthird lifetime prediction approachxe2x80x9d, the life of a semiconductor integrated circuit is supposed to expire when the total leakage current, increasing with the rise in number of SBD transistors, exceeds the reference level. Thus, supposing the number of SBD transistors is M when the total leakage current exceeds the reference level, the circuit""s lifetime can be predicted as a time that should pass after the stress started to be placed until the number of SBD transistors reaches M.
The present invention was made based on the above-described findings, or the xe2x80x9cthird lifetime prediction approachxe2x80x9d, in particular. Specifically, in a first inventive method of predicting the lifetime of a semiconductor integrated circuit, a time it takes for a total amount of B-mode stress induced leakage currents, flowing through respective MOS devices in the circuit, to reach a predetermined reference level is estimated as an expected lifetime of the circuit.
According to the first inventive lifetime prediction method, the lifetime of a semiconductor integrated circuit can be predicted without identifying the generation of a hard breakdown (HBD) in MOS devices. Thus, even if a thin gate insulating film, for which the HBD generation is nonidentifiable, is used for the MOS devices, the circuit""s lifetime can be predicted reliably.
Also, compared to regarding a time it takes for just one of MOS devices in a semiconductor integrated circuit to cause the SBD as the circuit""s lifetime (comparative example), the circuit""s lifetime, predicted by the first inventive method, can be closer to the actual one. Accordingly, if the thickness of a gate insulating film or a gate voltage for the MOS devices is adjusted to equalize the circuit""s lifetime, predicted by the first method, with a desired value, the gate insulating film will not be excessively thick or the gate voltage will not decrease unnecessarily. As a result, the circuit can be downsized and the operating speed of the MOS devices can be increased, thus enhancing the performance of the circuit.
A second inventive method of predicting the lifetime of a semiconductor integrated circuit includes: a first step of deriving, as a unit leakage current level, the amount of a B-mode stress induced leakage current flowing through each of SBD spots where a soft breakdown has occurred in multiple MOS devices included in the circuit; and a second step of obtaining a critical spot number from the unit leakage current level. The critical spot number is a minimum number of SBD spots required for a total amount of B-mode stress induced leakage currents, flowing through the respective MOS devices, to exceed a predetermined reference level. The second method further includes a third step of estimating, as an expected lifetime of the circuit, a time it takes for the number of SBD spots in the MOS devices to reach the critical spot number.
According to the second inventive lifetime prediction method, the first inventive lifetime prediction method is implementable just as intended. Thus, the same effects as those of the first inventive method are attainable without fail.
In the second inventive method, the third step preferably includes the steps of: obtaining a time T0 it takes for an MOS device under test, including a gate insulating film with an area S0, to cause a soft breakdown; and predicting the circuit""s lifetime by
TBSILC=T0xc3x97((Mxc3x97S0)/Schip)1/m
where TBSILC is the circuit""s lifetime, M is the critical spot number, Schip is a total area of the gate insulating films of the MOS devices and m is a form parameter in a Weibull distribution of the time T0.
In such an embodiment, the circuit""s lifetime can be predicted accurately.
In the second inventive method, the circuit is preferably virtually made up of a number N (which is a natural number) of MOS devices, each having a gate insulating film with an area STr. And the third step preferably includes the steps of: obtaining a time TSB(Tr) it takes for an MOS device under test, including a gate insulating film with the area STr, to cause a soft breakdown; and predicting the circuit""s lifetime by
TBSILC=TSB(Tr)xc3x97(M/N)1/m
where TBSILC is the circuit""s lifetime, M is the critical spot number and m is a form parameter in a Weibull distribution of the time TSB(Tr).
The circuit""s lifetime can also be predicted reliably enough by doing so.
In the second inventive method, the circuit is preferably virtually made up of a number N (which is a natural number) of MOS devices, each having a gate insulating film with an area STr. And the third step preferably includes the steps of: obtaining a time TSB(Tr) it takes for an MOS device under test, including a gate insulating film with the area STr, to cause a soft breakdown; and predicting the circuit""s lifetime by
TBSILC=TSB(Tr)xc3x97((Mxc3x97STr)/Schip)1/m
where TBSILC is the circuit""s lifetime, M is the critical spot number, Schip is a total area of the gate insulating films of the MOS devices and m is a form parameter in a Weibull distribution of the time TSB(Tr).
The circuit""s lifetime can also be predicted accurately enough by doing so.
In the second inventive method, the third step preferably includes the steps of: deriving a Weibull function for a time it takes for an MOS device under test to cause a soft breakdown; and predicting the circuit""s lifetime using a Weibull plot of the Weibull function.
The circuit""s lifetime can also be predicted accurately enough by doing so.
An inventive method for reliability testing of a semiconductor integrated circuit includes: a first step of estimating a first time it takes for a total amount of B-mode stress induced leakage currents, flowing through respective MOS devices in the circuit, to reach a predetermined reference level where an actual operating voltage is applied to the circuit; a second step of estimating a second time it takes for an MOS device under test to cause a soft breakdown from the first time where a test voltage, higher than the actual operating voltage, is applied thereto, and then determining, by the second time, a reference control level for a predetermined control point of the device under test; and a third step of measuring the control point of the device under test where the test voltage is applied thereto, and then determining whether or not a result of the measurement meets the reference control level.
According to the inventive reliability testing method, the reliability of a semiconductor integrated circuit can be tested using a first time it takes for a total amount of B-mode stress induced leakage currents, flowing through respective MOS devices, to reach a predetermined reference level at an actual operating voltage. That is to say, the reliability of the circuit can be tested using the circuit""s lifetime predicted by the first inventive lifetime prediction method at the actual operating voltage. Accordingly, even if a thin gate insulating film, for which the HBD generation is non-identifiable, is used for the MOS device, the reliability of the circuit can be tested just as intended.